Selective Growth for High-Aspect Ratio Metal Fill

ABSTRACT

An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.

PRIORITY

The present application is a divisional application of U.S. applicationSer. No. 16/166,412, filed on Oct. 22, 2018, which is a continuationapplication of U.S. application Ser. No. 15/290,509, filed on Oct. 11,2016, which is a divisional application of U.S. application Ser. No.14/588,223, filed on Dec. 31, 2014, which claims the benefit of U.S.Provisional Application Ser. No. 62/081,357, filed on Nov. 18, 2014,entitled “SELECTIVE GROWTH FOR HIGH-ASPECT RATIO METAL FILL,” each ofwhich is incorporated herein by reference in its entirety.

BACKGROUND

The semiconductor industry has progressed into nanometer technologyprocess nodes in pursuit of higher device density, higher performance,and lower cost. Despite groundbreaking advances in materials andfabrication, scaling planar device such as the conventional MOSFET hasproven challenging. As merely some examples, deposition techniques,etching techniques, and other processes that circulate liquids, gasses,or plasmas across device features perform well when the features arewidely spaced and accessible to the ambient reactants. However, narrowhigh-aspect ratio trenches and cavities restrict circulation and reducethe amount of reactants available within the trench. This may causeuneven deposition or etching within the trench.

To further push the state of the art, circuit designers are looking tonovel structures to deliver improved performance. One avenue of inquiryis the development of three-dimensional designs, such as a fin-likefield effect transistor (FinFET). A FinFET can be thought of as atypical planar device extruded out of a substrate and into the gate. Atypical FinFET is fabricated with a thin “fin” (or fin structure)extending up from a substrate. The channel of the FET is formed in thisvertical fin, and a gate is provided over (e.g., wrapping around) thechannel region of the fin. Wrapping the gate around the fin increasesthe contact area between the channel region and the gate and allows thegate to control the channel from multiple sides. This can be leveragedin a number of way, and in some applications, FinFETs provide reducedshort channel effects, reduced leakage, and higher current flow. Inother words, they may be faster, smaller, and more efficient than planardevices.

However, FinFETs and other nonplanar devices have even more complicatedgeometries and may have more high-aspect ratio trenches to fill.Accordingly, while conventional techniques for device fabrication havebeen adequate in some respects, they have been less than satisfactory inothers. In order to continue to meet ever-increasing designrequirements, further advances are needed in device fabrication andother areas. The present disclosure provides improvements that relate tothe fabrication of planar devices as well as FinFETs and other nonplanardevices.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detaileddescription when read with the accompanying figures. It is emphasizedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale and are used for illustration purposesonly. In fact, the dimensions of the various features may be arbitrarilyincreased or reduced for clarity of discussion. Also, several elementsand features are shown in the figures, not all of which are numbered forthe sake of clarity. It is understood, however, that symmetricalfeatures and items will be similarly situated.

FIG. 1 is a cross-sectional view of a semiconductor device according toembodiments of the present disclosure.

FIG. 2A is a perspective view of a nonplanar semiconductor deviceaccording to embodiments of the present disclosure.

FIG. 2B is a cross-sectional view of the nonplanar semiconductor device,where the cross-section is taken through a channel region, according toembodiments of the present disclosure.

FIG. 2C is a cross-sectional view of the nonplanar semiconductor device,where the cross-section is taken through a source/drain region,according to embodiments of the present disclosure.

FIG. 3 is a flow diagram of a method for forming a gate electrodeaccording to embodiments of the present disclosure.

FIGS. 4-11 are cross-sectional views of a portion of a nonplanar deviceundergoing the method of forming a gate electrode according toembodiments of the present disclosure.

FIGS. 12-19 are cross-sectional views of a portion of a planar deviceundergoing the method of forming a gate electrode according toembodiments of the present disclosure.

FIG. 20 a flow diagram of a method for forming a contact/via accordingto embodiments of the present disclosure.

FIGS. 21-26B are cross-sectional views of a portion of a planar deviceundergoing the method of forming a contact according to embodiments ofthe present disclosure.

FIGS. 27A and 27B are cross-sectional views of a source/drain region ofa nonplanar device undergoing the method of forming a contact accordingto embodiments of the present disclosure.

FIGS. 28A and 28B are cross-sectional views of a channel region of anonplanar device undergoing the method of forming a contact according toembodiments of the present disclosure.

FIGS. 29A and 29B are cross-sectional views of a semiconductor deviceundergoing the method of forming a via according to embodiments of thepresent disclosure.

DETAILED DESCRIPTION

The present disclosure relates generally to IC device manufacturing and,more particularly, to forming conductive features including devicegates, contacts, and vias.

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof various embodiments. Specific examples of components and arrangementsare described below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.Moreover, the formation of a first feature over or on a second featurein the description that follows may include embodiments in which thefirst and second features are formed in direct contact, and may alsoinclude embodiments in which additional features may be formedinterposing the first and second features, such that the first andsecond features may not be in direct contact.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. For example, if the device in the figures is turned over,elements described as being “below” or “beneath” other elements orfeatures would then be oriented “above” the other elements or features.Thus, the exemplary term “below” can encompass both an orientation ofabove and below. The apparatus may be otherwise oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein may likewise be interpreted accordingly.

A process is described for forming conductive features that offersimproved gap filling in high-aspect ratio trenches. The techniquereduces and even eliminates necking, voids, and discontinuities that mayoccur with other deposition techniques and is useful in forming devicegates, contacts, vias, and other structures. For context, FIG. 1 andFIGS. 2A-2C illustrate planar and nonplanar semiconductor devices andsome of the features thereof that may be formed by the process of thepresent disclosure. Of course, these features are merely exemplary, andthe technique may be used to form any suitable feature in any type ofdevice.

Referring first to FIG. 1, illustrated is a cross-sectional view of asemiconductor device 100 according to embodiments of the presentdisclosure. FIG. 1 has been simplified for the sake of clarity and tobetter illustrate the concepts of the present disclosure. Thesemiconductor device 100 is a typical of a planar MOSFET and isexemplary of both N-type metal-oxide-semiconductor transistor devices(referred to as NMOS devices) and P-type metal-oxide-semiconductortransistor devices (referred to as PMOS devices). The device 100 isformed on a substrate 102 such as a bulk silicon substrate.Alternatively, the substrate 102 may comprise an elementary (singleelement) semiconductor, such as silicon or germanium in a crystallinestructure; a compound semiconductor, such as silicon germanium, siliconcarbide, gallium arsenic, gallium phosphide, indium phosphide, indiumarsenide, and/or indium antimonide; and/or combinations thereof.Possible substrates 102 also include a silicon-on-insulator (SOI)substrate. SOI substrates are fabricated using separation byimplantation of oxygen (SIMOX), wafer bonding, and/or other suitablemethods. In other examples, the substrate 102 may include a multilayersemiconductor structure.

The substrate 102 may include various doped regions (e.g., p-type wellsor n-type wells), such as the illustrated source/drain regions 104. Thedoped regions may be doped with p-type dopants, such as phosphorus orarsenic, and/or n-type dopants, such as boron or BF₂ depending on designrequirements. The doped regions may be formed directly on the substrate,in a P-well structure, in an N-well structure, in a dual-well structure,or using a raised structure. Doped regions may be formed by implantationof dopant atoms, in-situ doped epitaxial growth, and/or other suitabletechniques. In some embodiments, the doped regions include halo/pocketregions that can reduce short channel effects (e.g., punch-througheffects) and may be formed by tilt-angle ion implantation or othersuitable technique.

The semiconductor device 100 may include a gate structure 106 disposedon the substrate between the source/drain regions 104. The flow ofcarriers (electrons for an n-channel device and holes for a p-channeldevice) through a channel region between the source/drain regions 104 iscontrolled by a voltage applied to the gate structure 106. Suitable gatestructures 106 include both polysilicon and metal gates. In anembodiment utilizing a gate first process, the gate structure 106 is afunctional gate. Conversely, in an embodiment utilizing a gate lastprocess, the gate structure 106 may be a functional gate or asacrificial (dummy) gate. In the exemplary gate last process, a portionof a sacrificial gate structure is removed and replaced with afunctional gate material, such as a metal, to form a functional gatestructure 106. The gate structure 106 may include multiple layers, andin the illustrated embodiment, the gate structure 106 includes aninterfacial layer (IL) 108, a dielectric layer 110, a capping layer 112,and a gate electrode 114. In some embodiments, sidewall spacers 116 areformed on one or more lateral surfaces of the gate structure.

To describe these features in more detail, the interfacial layer 108 isdisposed on the substrate 102 and may include an interfacial materialsuch as a silicon oxide, silicon nitride, silicon oxynitride, othersemiconductor oxides, other suitable interfacial materials, and/orcombinations thereof. The interfacial layer 108 may be formed to anysuitable thickness using any suitable process including thermal growth,atomic layer deposition (ALD), chemical vapor deposition (CVD),high-density plasma CVD (HDP-CVD), physical vapor deposition (PVD),spin-on deposition, and/or other suitable deposition processes.

The gate dielectric layer 110 is disposed on the interfacial layer 108and may comprise one or more dielectric materials, which are commonlycharacterized by their dielectric constant relative to silicon dioxide.Thus, the gate dielectric layer 110 may include a high-k dielectricmaterial such as HfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconiumoxide, aluminum oxide, hafnium dioxide-alumina (HfO₂-Al₂O₃) alloy, othersuitable high-k dielectric materials, and/or combinations thereof.Additionally or in the alternative, the gate dielectric layer 110 mayinclude other dielectrics such as silicon oxide, silicon nitride,silicon oxynitride, silicon carbide, amorphous carbon,tetraethylorthosilicate (TEOS), other suitable dielectric material,and/or combinations thereof. The gate dielectric layer 110 may be formedto any suitable thickness using any suitable process including ALD, CVD,HDP-CVD, PVD, spin-on deposition, and/or other suitable depositionprocesses.

The exemplary gate structure 106 may include a capping layer 112disposed on the gate dielectric layer 110. The capping layer 112 maycomprise silicon oxide, silicon nitride, silicon oxynitride, othersemiconductor oxides, other semiconductor nitrides, other suitablematerials, and/or combinations thereof.

A gate electrode 114 is disposed over the gate dielectric layer 110 andthe capping layer 112, if present. Despite naming conventions such asMOSFET, the semiconductor device 100 includes embodiments withpolysilicon-containing gate electrodes 114 as well as metal-containingelectrodes 114. The gate electrode 114 may have a multilayer structurethat includes one or more of an adhesion layer, a wetting layer, a linerlayer, and a metal fill layer. Accordingly, the gate electrode 114 mayinclude any suitable material, such as polysilicon, aluminum, copper,titanium, tantalum, tungsten, molybdenum, tantalum nitride, nickelsilicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metalalloys, other suitable materials, and/or combinations thereof.

In some embodiments utilizing a gate last process, the gate electrode114 contains a sacrificial (dummy) portion that includes polysilicon, adielectric, a masking material, and/or other suitable materials. In suchembodiments, the sacrificial portion may be removed in whole in or partby a suitable wet and/or dry etching process and replaced by anothergate electrode such as a metal-containing gate electrode 114. Asdescribed in more detail below, the deposition technique of the presentdisclosure is suitable for use in forming a metal gate in a recess leftby removing a sacrificial gate portion even where the high aspect ratio(ratio of depth to width) of the recess may pose difficulties forconventional deposition processes.

In some embodiments, gate spacers 116 or sidewall spacers are formed oneach side of the gate structure 106 (on the sidewalls of the gatestructure 106). The gate spacers 116 may be used to align thesource/drain regions 104 and may provide a rigid surface to preventtrench collapse during a gate replacement process. The gate spacers 116may include any suitable dielectric material, such as a semiconductoroxide, a semiconductor nitride, a semiconductor carbide, a semiconductoroxynitride, other suitable materials, and/or combinations thereof.

To integrate the semiconductor device 100 into a circuit, aninterconnect structure may be formed on the device 100. In theillustrated embodiment, the interconnect structure includes a number ofconductive traces 118 interspersed between layers of an inter-leveldielectric (ILD) 120. The ILD 120 may comprise any suitable dielectricmaterial, such as a semiconductor oxide, a semiconductor nitride, asemiconductor oxynitride, a semiconductor carbide, TEOS oxide,phosphosilicate glass (PSG), borophosphosilicate glass (BPSG),fluorinated silica glass (FSG), carbon doped silicon oxide, BlackDiamond®, Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB(bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Michigan),polyimide, other suitable materials, and/or combinations thereof. TheILD 120 layers act as an insulator that supports and isolates theconductive traces 118. Vias 122 extend through the ILD 120 layers toconnect conductive traces 118 at different horizontal locations, andcontacts 124 extend through the ILD 120 layers to connect tosource/drain regions 104, gate structures 106, and other features at ornear the substrate 102. As will be shown, the technique of the presentdisclosure is suitable for forming contacts 124 and vias 122. Of course,the contacts 124, vias 122, and the aforementioned gate electrode 114are merely some examples of device features that may be formed by thistechnique.

Whereas FIG. 1 highlights exemplary features of planar devices that maybe formed by the present technique, FIGS. 2A-2C, illustrate exemplaryfeatures of a nonplanar device that may be formed by the presenttechnique. FIG. 2A is a perspective view of a nonplanar semiconductordevice 200 according to embodiments of the present disclosure. FIG. 2Bis a cross-sectional view of a portion of the semiconductor device 200,where the cross-section is taken through a channel region (along plane202), according to embodiments of the present disclosure. FIG. 2C is across-sectional view of a portion of the semiconductor device 200, wherethe cross-section is taken through a source/drain region (along plane204), according to embodiments of the present disclosure. FIGS. 2A-2Chave been simplified for the sake of clarity and to better illustratethe concepts of the present disclosure.

Referring to FIGS. 2A-2C, the semiconductor device 200 includes asubstrate 102 or wafer with one or more fin structures 206 formed uponit. The fin structures 206 are representative of any raised feature, andwhile the illustrated embodiments include FinFET fin structures 206,further embodiments include other raised active and passive devicesformed upon the substrate 102. The illustrated fin structures 206 eachcomprise a pair of opposing source/drain regions 208, which may includevarious doped semiconductor materials, and a channel region 210 disposedbetween the source/drain regions 208. The flow of carriers through thechannel region 210 is controlled by a voltage applied to a gatestructure 212 adjacent to and overwrapping the channel region 210. Oneof the gate structures 212 is shown as translucent to better illustratethe underlying channel region 210. In the illustrated embodiment, thechannel region 210 rises above the plane of the substrate 102 upon whichit is formed, and accordingly, the fin structure 206 may be referred toas a “nonplanar” device. The raised channel region 210 provides a largersurface area proximate to the gate structure 212 than in comparableplanar devices. This strengthens the electromagnetic field interactionsbetween the gate structure 212 and the channel region 210, which mayreduce leakage and short channel effects associated with smallerdevices. Thus in many embodiments, FinFETs and other nonplanar devicesdeliver better performance in a smaller footprint than their planarcounterparts.

The elements of the semiconductor device 200 will now be described inadditional detail. Substrate 102 may be substantially similar to thesubstrate 102 of FIG. 1 and may include any suitable semiconductorand/or non-semiconductor material. For example, the substrate 102 mayinclude one or more layers of an elementary semiconductor, such assilicon or germanium; a compound semiconductor, such as silicongermanium, silicon carbide, gallium arsenic, gallium phosphide, indiumphosphide, indium arsenide, and/or indium antimonide; anon-semiconductor material, such as soda-lime glass, fused silica, fusedquartz, calcium fluoride (CaF₂); other suitable materials; and/orcombinations thereof.

The fin structures 206 are formed on the substrate 102 by recessingsurrounding portions of the substrate 102 and leaving the fin structures206 and/or by depositing material to grow the fin structures 206 on thesubstrate 102. After a gate structure 212 is formed to protect thechannel regions 210 of the fin structures, additional semiconductormaterial may be added to the source/drain regions 208 of the finstructure 206. In many embodiments, the additional material is depositedby one or more epitaxy or epitaxial (epi) processes, whereby Sifeatures, SiGe features, and/or other suitable features are grown in acrystalline state on the fin structure 206. Suitable epitaxy processesinclude CVD deposition techniques (e.g., vapor-phase epitaxy (VPE)and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/orother suitable processes. The material of the source/drain regions 208may be in-situ doped during the epitaxy process by introducing dopingspecies including: p-type dopants, such as boron or BF₂; n-type dopants,such as phosphorus or arsenic; and/or other suitable dopants includingcombinations thereof. If the source/drain regions 208 are not in-situdoped, an implantation process (i.e., a junction implant process) isperformed to dope the regions 208.

The gate structure 212 is formed on top of one or more of the finstructures 206 and may include an interfacial layer 214, a gatedielectric layer 216, a capping layer 218, and a gate electrode 220disposed on and overwrapping the channel region 210 of the finstructures 206. Each of these elements may be substantially similar totheir planar device counterparts in composition. For example, theinterfacial layer 214 may include an oxide, HfSiO, a nitride, anoxynitride, and/or other suitable material and may be deposited by anysuitable method, such as thermal oxidation, ALD, CVD, ozone oxidation,etc. The gate dielectric layer 216 may include any suitable dielectricsuch as a high-k dielectric material including: LaO, AlO, ZrO, TiO,Ta₂O₅, Y₂O₃, SrTiO₃ (STO), BaTiO₃ (BTO), BaZrO, HfZrO, HfLaO, HfSiO,LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO₃ (BST), Al₂O₃, Si₃N₄, oxynitrides(SiON), and/or other suitable materials. The capping layer 218 maycomprise silicon oxide, silicon nitride, silicon oxynitride, othersemiconductor oxides, other semiconductor nitrides, other suitablematerials, and/or combinations thereof.

The gate electrode 220 is disposed on the gate dielectric layer 216 andon the capping layer 218, if present, and in various examples, containspolysilicon, metals, metal alloys, metal compounds, and/or non-metallicconductors. Suitable metals include W, Al, Cu, Ti, Ag, TiAlN, TaC, TaCN,TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, and/or any other suitablematerials. In some embodiments, different gate materials are used fornMOS and pMOS devices. The gate electrode 220 may have a multilayerstructure that includes one or more of an adhesion layer, a wettinglayer, a liner layer, and a metal fill layer. As with the planar device,the technique of the present disclosure may be used to form the gateelectrode 220 as part of a gate replacement process or othergate-forming technique.

The gate structure 212 may also include one or more sidewall spacinglayers 222, of which two are shown. Suitable materials for the sidewallspacing layers 222 include dielectrics such as semiconductor oxides,semiconductor nitrides, semiconductor oxynitrides, semiconductorcarbides, and/or other dielectrics. In some examples, the sidewallspacing layers 2220 include alternating layers of different dielectricssuch as a first semiconductor oxide spacing layer and a secondsemiconductor nitride spacing layer. Any of a number of techniques maybe used to form the sidewall spacing layers 222 including CVD, PVD, ALD,and/or other suitable deposition techniques.

Similar to the exemplary planar device, an interconnect structure isdisposed on the substrate 102 and on the gate structure 212 thatincludes a number of conductive traces 118 interspersed between layersof an inter-level dielectric (ILD) 120. For clarity, the interconnectstructure is not illustrated in FIG. 2A to avoid obscuring otherfeatures. As in the planar example of FIG. 1, the technique of thepresent disclosure is suitable for forming contacts 124 and vias 122within the interconnect structure of nonplanar device 200.

An application using the present technique to form a gate electrode isdescribed with reference to FIGS. 3-11. FIG. 3 is a flow diagram of themethod 300 for forming a gate electrode according to embodiments of thepresent disclosure. It is understood that additional steps can beprovided before, during, and after the method 300 and that some of thesteps described can be replaced or eliminated for other embodiments ofthe method 300. FIGS. 4-11 are cross-sectional views of a portion of anonplanar device 200 undergoing the method 300 of forming the gateelectrode according to embodiments of the present disclosure. Examplesthat apply the method 300 to a planar device are described withreference to later figures.

Referring to block 302 of FIG. 3 and to FIG. 4, a substrate 102 isreceived that includes a semiconductor device 200. The substrate 102 andthe semiconductor device 200 may each be substantially similar to thoseof FIGS. 2A-2C, and in the interest of brevity, similar elements thereofare not described again. In the embodiment of FIG. 4, the semiconductordevice 200 includes a portion of a gate structure 212 substantiallysimilar to that of FIG. 2A. The gate structure includes a sacrificialgate electrode 402, which may include polysilicon, a dielectric, amasking material, and/or other suitable materials. Referring to block304 of FIG. 3 and to FIG. 5, the sacrificial gate electrode 402 isremoved leaving a trench 404 defined by the sidewall spacing layers 222.Due in part to the geometry of the trench 404, forming layers within thetrench 404 may prove challenging. For example, the trench 404 may have ahigh aspect ratio and/or narrow interior cavities where depositionreactants do not circulate well.

A gate dielectric layer 216 of the gate structure 212 may be formedeither before or after the sacrificial gate electrode 402 is removed. Inthe example of block 306 of FIG. 3 and FIG. 6, the gate dielectric layer216 is formed within the trench 404 after the sacrificial gate electrode402 is removed. In the illustrated embodiment, the gate dielectric layer216 is formed on the interfacial layer 214 in the trench 404 and alsoextends along the vertical surfaces of the sidewall spacing layers 222such that the portions of the gate dielectric layer 216 on the verticalsurfaces extend above the portions of the gate dielectric layer 216 onthe interfacial layer 214. This forms a U-shaped structure. In someembodiments, a highly-conformal deposition technique such as CVD or ALDis used to deposit the gate dielectric layer 216 in the U-shapedconfiguration, although non-conformal deposition techniques may also beused. In these embodiments and others, suitable deposition processesinclude CVD, high-density plasma CVD (HDP-CVD), ALD, PVD, spin-ondeposition, and/or other suitable deposition processes. The gatedielectric layer 216 may be similar in composition to those of FIGS.1-2C.

A work function layer 406 of the gate structure 212 may also be formedeither before or after the sacrificial gate electrode 402 is removed. Inthe example of block 308 of FIG. 3 and FIG. 6, the work function layer406 is formed on the gate dielectric layer 216 within the trench 404after the sacrificial gate electrode 402 is removed. The work functionlayer 406 may be used to tune the threshold voltage of the resultingsemiconductor device and, to that end, may include a material specificto the type of device 200 being formed (e.g., n-type work functionmaterial for an n-type device, p-type work function material for ap-type device). Exemplary p-type work function metals include TiN, TaN,Ru, Mo, Al, WN, ZrSi₂, MoSi₂, TaSi₂, NiSi₂, WN, other suitable p-typework function materials, and/or combinations thereof. Exemplary n-typework function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN,TaSiN, Mn, Zr, other suitable n-type work function materials, and/orcombinations thereof. The work function layer 406 may include aplurality of layers and may be deposited by CVD, PVD, and/or othersuitable process to any suitable thickness. In the illustratedembodiment, the work function layer 406 extends along the verticalsurfaces of the gate dielectric layer 216 to form a U-shaped structure.

Referring to block 310 of FIG. 3 and to FIG. 7, a wetting layer 408 maybe deposited on the gate dielectric layer 216 and/or the work functionlayer 406. The wetting layer 408 promotes bonding between the layers andmay promote uniform deposition of the subsequent layers. In variousexamples, the wetting layer 408 includes Ti, Ta, Ni, Co, other metals,and/or combinations thereof. The wetting layer 408 may be formed withinthe trench 404 using any suitable deposition technique including ALD,CVD, and/or sputtering and may be formed to any suitable thickness.

Referring to block 310 of FIG. 3 and to FIG. 8, a barrier layer 410 maybe deposited on the wetting layer 408. The barrier layer 410 may bestructured to prevent subsequent deposition processes from degradingother layers of the device 200. For example, some metals have a tendencyto diffuse into silicon-containing layers during deposition and evenafter fabrication has completed. Accordingly, the barrier layer 410 mayinclude TiN, TaN, and/or other suitable metals, metal oxides and/ormetal nitrides. Similar to the wetting layer 408, the barrier layer 410may be deposited within the trench 404 using any suitable processincluding ALD, CVD, and/or sputtering and may be deposited to anysuitable thickness. In some embodiments, a single deposition stepdeposits a metal common to both the wetting layer 408 and the barrierlayer 410. The metal of the barrier layer 410 may then undergo anoxidation, nitridation, or other process to form an oxide, nitride,and/or other metal compound in the barrier layer 410.

While a fill material may be deposited directly on the barrier layer410, it is been determined that as the aspect ratio of the trench 404becomes larger, even conformal deposition processes tend to depositmaterial faster near the top of the trench 404. This may result in thetopmost portion of the trench 404 closing off while a void still existsin a bottom portion of the trench 404. This tendency to create voidsbecomes particularly acute as trench aspect ratios approach or exceed10:1 (depth:width), although it is seen at much lower aspect ratios aswell. Accordingly, in some embodiments, a growth control layer 412 isformed on the opposing trench side surfaces 414 but not necessarily thetrench bottom 416. This is shown in block 314 of FIG. 3 and FIGS. 9A and9B. The growth control layer 412 affects the deposition rate of thetechnique used to subsequently deposit the fill material. In anexemplary embodiment, the growth control layer 412 reduces thedeposition rate on the trench side surfaces 414 relative to the rate onthe trench bottom 416, so that an otherwise conformal depositiontechnique fills the bottom of the trench 404 faster than the top. Inother words, the growth control layer 412 causes an ALD, CVD,sputtering, and/or other conformal deposition process to fill the trench404 from the bottom up.

The growth control layer 412 may contain any suitable metal, metaloxide, metal carbide, metal nitride, and/or combination thereof and maybe different in composition from the barrier layer 410, for example. Invarious embodiments, the growth control layer 412 contains WC, WN, AlC,AlN, and/or other suitable materials. In some embodiments, one or moremetal constituents of the growth control layer 412 are selected to matchmetal components of the subsequently deposited fill material 418. Insome such embodiments, WC or WN is selected for the growth control layer412 based on a W-containing fill material 418. In further suchembodiments, AlC or AN is selected for the growth control layer 412based on an Al-containing fill material 418.

The growth control layer 412 may be deposited to any thickness (measuredperpendicular to the side surfaces 414), although for materials withlower conductivity, the growth control layer 412 may be quite thin(e.g., between about 1 Å and about 20 Å at its thickest). The growthcontrol layer 412 extends along at least the upper portions of the sidesurfaces 414 and may extend all the way to the bottom surface 416 asshown in FIG. 9B. Due to the growth control layer 412, the bottomsurface 416 of the trench 404 has a different composition from thetrench sidewalls defined by the growth control layer 412. Thisdifference may be used to tune subsequent deposition processes.

Any suitable conformal or non-conformal deposition may be used to formthe growth control layer 412. In various embodiments, ALD, CVD,sputtering, and/or other suitable techniques are used to form the growthcontrol layer 412 on the side surfaces 414. In one such embodiment, ametal component of the growth control layer 412 is deposited via ALD anda subsequent plasma treatment is performed using a nitrogen-containingand/or carbon-containing gas to form a metal nitride and/or metalcarbide. Even though some of these deposition techniques are conformalin most applications, in such embodiments, the geometry of the trench404 may prevent the reactants from reaching the bottom of the trench404. Thus, these techniques may deposit material on the side surfaces414 faster than the bottom surface 416, which turns the difficulty offilling the trench bottom 416 into an advantage. Deposition may befollowed by an anisotropic etching process to remove any depositedmaterial from the bottom surface 416 of the trench 404. For example, inan embodiment, the growth control layer 412 is deposited by sputteringfollowed by an anisotropic dry etch that targets deposited material onthe bottom surface 416.

Referring to block 316 of FIG. 3 and to FIGS. 10 and 11, a fill material418 of the gate electrode 220 may be deposited within the trench 404 onthe growth control layer 412. FIG. 10 corresponds to the embodiments ofFIG. 9A where the growth control layer 412 does not extend to the bottomsurface 416, while FIG. 11 corresponds to the embodiments of FIG. 9Bwhere the growth control layer 412 does extend to the bottom surface416. The fill material 418 may include any suitable conductor includingW, Al, Cu, Ti, Ag, Ru, Mo, other suitable metals and alloys thereof. Thefill material 418 may be formed using any suitable technique includingALD, CVD, and/or sputtering. Due in part to the growth control layer412, the fill material 418 may be deposited on the bottom surface 416 ofthe trench 404 faster than it is deposited on the side surfaces 414. Ina particular application, a metal carbide growth control layer 412reduces the deposition rate on the side surfaces 414 by a factor of 10.It has been determined through experimentation and analysis that fillinghigh-aspect ratio trenches 404 in this manner greatly reduces theoccurrences of voids and other defects in the fill material 418.

Referring to block 318 of FIG. 3, a planarization technique such aschemical mechanical planarization/polishing (CMP) may be performed onthe semiconductor device 200 to remove excess materials extending beyondthe trench 404. Referring to block 320 of FIG. 3, the device 200 may beprovided for further fabrication.

The method 300 may also be used to form a gate electrode in a planardevice as described with reference to FIGS. 3 and FIGS. 12-19. FIGS.12-19 are cross-sectional views of a portion of a nonplanar device 100undergoing the method 300 of forming a gate electrode according toembodiments of the present disclosure.

Referring to block 302 of FIG. 3 and to FIG. 12, a substrate 102 isreceived that includes a semiconductor device 100. The substrate 102 andthe semiconductor device 100 may each be substantially similar to thoseof FIG. 1, and in the interest of brevity, similar elements thereof arenot described again. In the embodiment of FIG. 12, the semiconductordevice 100 includes a portion of a gate structure 116 substantiallysimilar to that of FIG. 1 that includes a sacrificial gate electrode402. The sacrificial gate electrode 402 may include polysilicon, adielectric, a masking material, and/or other suitable materials.Referring to block 304 of FIG. 3 and to FIG. 13, the sacrificial gateelectrode 402 is removed leaving a trench 404 defined by the sidewallspacers 116. Due in part to the geometry of the trench 404, forminglayers within may prove challenging. For example, the trench 404 mayhave a high aspect ratio and/or narrow interior cavities wheredeposition reactants do not circulate as well.

A gate dielectric layer 110 may be formed either before or after thesacrificial gate electrode 402 is removed. Accordingly, in block 306 ofFIG. 3 and FIG. 14, the gate dielectric layer 110 is formed within thetrench 404 after the sacrificial gate electrode 402 is removed. In theillustrated embodiment, the gate dielectric layer 110 is formed on theinterfacial layer 108 in the trench 404 and also extends along thevertical surfaces of the sidewall spacers 116 to form a U-shaped layer.Suitable deposition processes include CVD, high-density plasma CVD(HDP-CVD), ALD, PVD, spin-on deposition, and/or other suitabledeposition processes, and the gate dielectric layer 110 may be similarin composition to those of FIGS. 1-2C.

A work function layer 406 may also be formed either before or after thesacrificial gate electrode 402 is removed. In the example of block 308of FIG. 3 and FIG. 14, the work function layer 406 is formed on the gatedielectric layer 110 within the trench 404 after the sacrificial gateelectrode 402 is removed. The work function layer 406 may include amaterial tuned to the particular type of device 100 being formed and maybe similar in composition to the work function layer 406 of FIG. 4. Inthe illustrated embodiment, the work function layer 406 extends alongthe vertical surfaces of the gate dielectric layer 110 to form aU-shape. The work function layer 406 may include a plurality of layersand may be deposited by CVD, PVD, and/or other suitable process to anysuitable thickness.

Referring to block 310 of FIG. 3 and to FIG. 15, a wetting layer 408 maybe deposited on the gate dielectric layer 110 and/or the work functionlayer 406. The wetting layer 408 may include Ti, Ta, Ni, Co, othermetals, and/or combinations thereof and may be formed by any suitabletechnique including ALD, CVD, or sputtering. The wetting layer 408 maybe formed within the trench 404 using any suitable deposition techniqueincluding ALD, CVD, and/or sputtering and may be formed to any suitablethickness.

Referring to block 312 of FIG. 3 and to FIG. 16, a barrier layer 410 maybe deposited on the wetting layer 408. The barrier layer 410 may includeTiN, TaN, and/or other suitable metals, metal oxides and/or metalnitrides and may be deposited by any suitable technique including ALD,CVD, and/or sputtering. In some embodiments, a single deposition stepdeposits a metal common to both the wetting layer 408 and the barrierlayer 410. The metal of the barrier layer 410 may then undergo anoxidation, nitridation, or other process to form an oxide, nitride,and/or other metal compound in the barrier layer 410.

Referring to block 314 of FIG. 3 and FIGS. 17A and 17B, a growth controllayer 412 is formed on the trench side surfaces 414 but not necessarilythe trench bottom 416. The growth control layer 412 affects thedeposition rate of the technique used to subsequently deposit the fillmaterial. Accordingly, the growth control layer 412 may contain anysuitable metal, metal oxide, metal carbide, metal nitride, and/orcombination thereof. For example, the growth control layer 412 maycontain WC, WN, AlC, AN, and/or other suitable materials. In someembodiments, one or more metal constituents of the growth control layer412 are selected to match metal components of the subsequently depositedfill material 418.

The growth control layer 412 may be deposited to any thickness (measuredperpendicular to the side surfaces 414), and for materials with lowerconductivity, the growth control layer 412 may be quite thin (e.g.,between about 1 Å and about 20 Å at its thickest). The growth controllayer 412 extends along at least the upper portions of the side surfaces414 and may extend all the way to the bottom surface 416 as shown inFIG. 17B. Due to the growth control layer 412, the bottom surface 416 ofthe trench 404 has a different composition from the trench sidewallsdefined by the growth control layer 412. This difference may be used totune subsequent deposition processes.

Any suitable conformal or non-conformal deposition may be used to formthe growth control layer 412. In various embodiments, ALD, CVD,sputtering, and/or other suitable techniques are used to form the growthcontrol layer 412 on the side surfaces 414. In one such embodiment, ametal component of the growth control layer 412 is deposited via ALD anda subsequent plasma treatment is performed using a nitrogen-containingand/or carbon-containing gas to form a metal nitride and/or metalcarbide. In some applications, conformal deposition techniques rely onthe geometry of the trench 404 to prevent reactants from reaching thebottom 416 of the trench 404. Deposition may be followed by, ananisotropic etching process to remove any deposited material from thebottom surface 416 of the trench 404. For example, in an embodiment, thegrowth control layer 412 is deposited by sputtering followed by ananisotropic dry etch that targets deposited material on the bottomsurface 416.

Referring to block 316 of FIG. 3 and to FIGS. 18 and 19, a fill material418 of the gate electrode 116 may be deposited within the trench 404 onthe growth control layer 412. FIG. 18 corresponds to the embodiments ofFIG. 17A where the growth control layer 412 does not extend to thebottom surface 416, while FIG. 19 corresponds to the embodiments of FIG.17B where the growth control layer 412 does extend to the bottom surface416. The fill material 418 may include any suitable conductor includingW, Al, Cu, Ti, Ag, Ru, Mo, other suitable metals and alloys thereof. Thefill material 418 may be formed using any suitable technique includingALD, CVD, and/or sputtering. Due in part to the growth control layer 412the fill material 418 may be deposited on the bottom surface 416 of thetrench 404 faster than it is deposited on the side surfaces 414. It hasbeen determined that filling high-aspect ratio trenches 404 in thismanner greatly reduces the occurrences of voids and other defects in thefill material 418.

Referring to block 318 of FIG. 3, a planarization technique such aschemical mechanical planarization/polishing (CMP) may be performed onthe semiconductor device 100 to remove excess materials extending beyondthe trench 404. Referring to block 320 of FIG. 3, the device 100 may beprovided for further fabrication.

As described above the techniques of the present disclosure may also beused to form contacts and vias. Examples of which are described withreference to FIGS. 20-29B. FIG. 20 is a flow diagram of the method 2000for forming a contact/via according to embodiments of the presentdisclosure. It is understood that additional steps can be providedbefore, during, and after the method 2000 and that some of the stepsdescribed can be replaced or eliminated for other embodiments of themethod 2000. FIGS. 21-26 are cross-sectional views of a portion of adevice 100 undergoing the method 2000 of forming a contact/via accordingto embodiments of the present disclosure. FIGS. 27A and 27B arecross-sectional views of a source/drain region of a nonplanar device 200having undergone the method 2000 according to embodiments of the presentdisclosure. FIGS. 28A and 28B are cross-sectional views of a channelregion of a nonplanar device 200 having undergone the method 2000according to embodiments of the present disclosure. FIGS. 29A and 29Bare cross-sectional views of a semiconductor device 2900 havingundergone the method according to embodiments of the present disclosure.

Referring to block 2002 of FIG. 20 and to FIG. 21, a substrate 102 isreceived that includes a semiconductor device 100. The substrate 102 andthe semiconductor device 100 may each be substantially similar to thoseof FIG. 1, and in the interest of brevity, similar elements thereof arenot described again. In the illustrated embodiment, the semiconductordevice 100 includes one or more layers of an ILD 120 disposed on thesource/drain regions 104 and on the gate structure 116. Referring toblock 2004 of FIG. 20 and referring still to FIG. 21, a patterned layer2102, such as a photoresist layer, is formed on the ILD 120 andpatterned to expose contact/via regions. In embodiment of FIG. 21, theexposed contact/via regions, correspond to contact regions. Thepatterned layer 2102 may be patterned by any direct-write,photolithographic, and/or other suitable process, and in an exemplaryembodiment, selected regions of the patterned layer 2102 are exposed tophotolithographic radiation causing a photoactive chemical in thepatterned layer 2102 to undergo a chemical reaction. A developmentprocess is performed that relies on the result of the chemical reactionto selectively remove exposed or unexposed regions of the patternedlayer 2102.

Referring to block 2006 of FIG. 20 and to FIG. 22, the ILD layer(s) 120are etched using the patterned layer 2102 to selectively etch thecontact/via recesses such as the contact recesses 2202 of FIG. 22. Theetching of the ILD layer 120 may include any suitable etching techniqueincluding wet etching, dry etching, reactive ion etching (RIE), etc.,and may use any suitable etch chemistry or combination thereof. In anexemplary embodiment, the etching of block 2006 includes a first etchthat utilizes a directional, or anisotropic, etching technique to form avertical recess and a second etch that utilizes a non-directional, orisotropic, etching technique to widen the recess. The remainingpatterned layer 2102 may be removed after the ILD layer(s) 120 areetched.

Referring to block 2008 of FIG. 20 and to FIG. 23, an adhesion layer2302 formed on the ILD and within the etched portions of the patternedlayer 2102. As the name implies, the adhesion layer 2302 may be used toimprove the quality of the interface between the existing materials,including the ILD layers 120, the source/drain regions 104, and the gatestructure 116 and subsequently deposited materials such as a fillmaterial of the contacts/vias. Accordingly, the adhesion layer 2302 mayinclude one or more layers of conductive materials including metals(e.g., Ti, Ta, W, Al, Ni, Cu, Co, etc.) and metal nitrides, which may bedeposited via ALD, CVD, PE CVD, PEALD, PVD, and/or other suitabledeposition process. In the present embodiment, the adhesion layer 2302includes multiple deposited layers of Ti and TiN. In other embodiments,one or more additional layers are added, such as barrier layers.

While the contacts 124 may be formed by depositing a fill materialdirectly on the adhesion layer 2302, it is been determined that as theaspect ratio of the contact/via recess becomes larger, voids anddiscontinuities may occur similar to those described in the context ofmetal gate fill techniques. Accordingly, referring to block 2010 of FIG.20 and to FIGS. 24A and 24B, in some embodiments, a growth control layer2402 is formed on the side surfaces 2404 of the recess but notnecessarily the bottom surface 2406. The growth control layer 2402 maycover only topmost a portion of the side surfaces 2404 as shown in FIG.24A or may extend to the bottom surface 2406 as shown in FIG. 24B. Thegrowth control layer 2402 affects the deposition rate of the techniqueused to subsequently deposit the fill material and may reduce thedeposition rate on the recess side surfaces 2404, so that an otherwiseconformal deposition technique fills the bottom of the recess fasterthan the top.

The growth control layer 2402 may contain any suitable metal, metaloxide, metal carbide, metal nitride, and/or combination thereof and maybe different in composition from the adhesion layer 2303, for example.In various embodiments, the growth control layer 2402 contains WC, WN,AlC, AN, and/or other suitable materials. In some embodiments, one ormore metal constituents of the growth control layer 2402 are selected tomatch metal components of the subsequently deposited fill material. Insome such embodiments, WC or WN is selected for the growth control layer2402 based on a W-containing fill material. In further such embodiments,AlC or AN is selected for the growth control layer 2402 based on anAl-containing fill material.

The growth control layer 2402 may be deposited to any thickness(measured perpendicular to the side surfaces 2404), although formaterials with lower conductivity, the growth control layer 2402 may bequite thin (e.g., between about 1 Å and about 20 Å at its thickest). Asa result of the growth control layer 2402, the bottom surface 2406 ofthe recess has a different composition from at the recess sidewallsdefined by the growth control layer 2402. This difference may be used totune subsequent deposition processes.

Any suitable conformal or non-conformal deposition may be used to formthe growth control layer 2402. In various embodiments, ALD, CVD,sputtering, and/or other suitable techniques are used to form the growthcontrol layer 2402 on the side surfaces 2404. In one such embodiment, ametal component of the growth control layer 2402 is deposited via ALDand a subsequent plasma treatment is performed using anitrogen-containing and/or carbon-containing gas to form a metal nitrideand/or metal carbide. Deposition may be followed by an anisotropicetching process to remove any deposited material from the bottom surface2406 of the recess 2202. For example, in an embodiment, the growthcontrol layer 2402 is deposited by sputtering followed by an anisotropicdry etch that targets deposited material on the bottom surface 2406.

Referring to block 2012 of FIG. 20 and to FIG. 25, a fill material 2502of the contact/via may be deposited within the recess on the growthcontrol layer 2402. The fill material 2502 may include any suitableconductor including metals (e.g., W, Al, Ta, Ti, Ni, Cu, etc.), metaloxides, metal nitrides, and/or combinations thereof. The contact fillmaterial 307 may be deposited by any suitable technique including PVD(e.g., sputtering), CVD, PE CVD, ALD, PEALD, and/or combinationsthereof. Due in part to the growth control layer 2402 the fill material2502 may be deposited on the bottom surface 2406 of the recess 2202faster than it is deposited on the side surfaces 2404. It has beendetermined through experimentation and analysis that filling high-aspectratio recesses in this manner greatly reduces the occurrences of voidsand other defects in the fill material 2502.

Referring to block 2014 of FIG. 20 and to FIGS. 26A and 26B, aplanarization technique such as chemical mechanicalplanarization/polishing (CMP) may be performed on the semiconductordevice 100 to remove excess materials extending beyond the recesses.FIG. 26A corresponds to the embodiments of FIG. 24A where the growthcontrol layer 2402 does not extend to the bottom surface 2406, whileFIG. 26B corresponds to the embodiments of FIG. 24B where the growthcontrol layer 2402 does extend to the bottom surface 2406. Referring toblock 2016 of FIG. 20, the device 100 may be provided for furtherfabrication.

Other examples of contacts and vias that may be formed by the method2000 are shown in FIGS. 27A-29B. Referring first to FIGS. 27A and 27B,exemplary contacts 124 to source/drain regions 208 of a nonplanar device200 formed by the present techniques are disclosed. In many aspects, thenonplanar device 200 is substantially similar to that of FIGS. 2A-2C,and in the interest of brevity, similar structures may not be repeated.

In the illustrated embodiment, the contacts 124 extend into the ILD 120in the vertical direction and span one or more source/drain regions 208in the horizontal direction. Accordingly, an adhesion layer 2302 of thecontacts 124, substantially similar to that of FIG. 23, is disposed onat least one surface of at least one source/drain region 208 using atechnique such as that of block 2008 of FIG. 20. The adhesion layer 2302may also be disposed on the substrate 102 between the source/drainregions 208.

The contact 124 further includes a growth control layer 2402 formed by aprocess such as that of block 2010 of FIG. 20. The growth control layer2402 is disposed on the side surfaces 2404 of the trench, but notnecessarily on the substrate 102 at the bottom surface 2406. Dependingon the application, the growth control layer 2402 may be disposed on thesource/drain regions 208 as shown in FIG. 27A or may be omitted in theseregions as shown in FIG. 27B. A fill material 2502, such as the fillmaterial 2502 of FIG. 25 is disposed on the growth control layer 2402 tocomplete the contact 124.

Referring to FIGS. 28A and 28B, exemplary contacts 124 to a gatestructure 212 of a nonplanar device 200 formed by the present techniquesare disclosed. In many aspects, the nonplanar device 200 issubstantially similar to that of FIGS. 2A-2C, and in the interest ofbrevity, similar structures may not be repeated. The contacts 124include an adhesion layer 2302 substantially similar to that of FIG. 23.The adhesion layer 2302 is disposed within a recess formed in the ILD120 over the gate structure 212 using a technique such as that of block2008 of FIG. 20.

The contact 124 also includes a growth control layer 2402 formed by aprocess such as that of block 2010 of FIG. 20. The growth control layer2402 is disposed on the side surfaces 2404 of the trench, but notnecessarily on the trench bottom so that the different composition ofresulting sidewalls can be used to tune subsequent deposition processes.Depending on the application, the growth control layer 2402 extendsalong at least the upper portions of the side surfaces 2404 as shown inFIG. 28A and may extend all the way to bottom surfaces (e.g., theadhesion layer 2302 on the gate structure 212) as shown in FIG. 28B. Afill material 2502, such as the fill material 2502 of FIG. 25 isdisposed on the growth control layer 2402 to complete the contact 124.

Finally, referring to FIGS. 29A and 29B, the method 2000 may be used toform vias 122. FIGS. 29A and 29B are cross-sectional diagrams of aninterconnect structure of a semiconductor device 2900 such as a planaror non-planar semiconductor device according to embodiments of thepresent disclosure. Similar to the contacts 124, the vias 122 mayinclude an adhesion layer 2302 substantially similar to that of FIG. 23.The adhesion layer 2302 is disposed within a recess formed in the ILD120 using a technique such as that of block 2008 of FIG. 20. Theadhesion layer 2302 may contact an underlying conductive trace 118.

The vias 122 include a growth control layer 2402 formed by a processsuch as that of block 2010 of FIG. 20. The growth control layer 2402 isdisposed on the side surfaces 2404 of the recess, but not necessarily onbottom surface 2406 so that the different composition of the resultingsidewalls can be used to tune subsequent deposition processes. Dependingon the application, the growth control layer 2402 extends along at leastthe upper portions of the side surfaces 2404 as shown in FIG. 29A andmay extend all the way to the adhesion layer 2302 on the gate structure212 as shown in FIG. 29B. A fill material 2502, such as the fillmaterial 2502 of FIG. 25 is disposed on the growth control layer 2402 tocomplete the via 122 and in some embodiments, to form conductive traces118.

Accordingly, a technique for forming conductive features is provided,and the structures produced by the technique are disclosed. In someembodiments, the method includes receiving a substrate with a gatestructure. The gate structure includes a sacrificial portion that isremoved to define a trench within the gate structure. The trench hasopposing side surfaces and a bottom surface defined thereupon. Amaterial layer is selectively formed on the opposing side surfaces suchthat the bottom surface is free of the material layer. A fill materialof a gate electrode is deposited on the material layer and on the bottomsurface within the trench. In some such embodiments, the forming of thematerial layer includes depositing a metal using atomic layer deposition(ALD) and performing a plasma treatment of the metal using acarbon-containing gas. In some such embodiments, the forming of thematerial layer includes a deposition process and an etching processconfigured to remove deposited material from the bottom surface.

In further embodiments, the method includes receiving a substrate havinga recess defined by at least two opposing sidewalls and a bottomsurface. A growth control material is deposited within the recess and onthe at least two opposing sidewalls such that the bottom surface is freeof the growth control material. A fill material layer is depositedwithin the recess such that the fill material is on the growth controlmaterial and on the bottom surface. In some such embodiments, the growthcontrol material includes at least one of a metal nitride or a metalcarbide. In some such embodiments, the growth control material and thefill material layer include at least one metal in common.

In yet further embodiments, the semiconductor device comprises asubstrate having a gate structure formed thereupon. The gate structureincludes a gate dielectric layer disposed on the substrate, a growthcontrol material disposed on a side surface of the gate structure, and agate electrode fill material disposed on the growth control material andon a bottom surface that is free of the growth control material. In someembodiments, the gate structure further includes a barrier layerdisposed between the growth control material and the gate dielectriclayer and between the gate electrode fill material and the gatedielectric layer. In some of these embodiments, the barrier layer isdifferent in composition from the growth control material. In someembodiments, the gate electrode fill material contacts a first surfaceand a second surface that are different in composition.

The foregoing has outlined features of several embodiments. Thoseskilled in the art should appreciate that they may readily use thepresent disclosure as a basis for designing or modifying other processesand structures for carrying out the same purposes and/or achieving thesame advantages of the embodiments introduced herein. Those skilled inthe art should also realize that such equivalent constructions do notdepart from the spirit and scope of the present disclosure, and thatthey may make various changes, substitutions and alterations hereinwithout departing from the spirit and scope of the present disclosure.

What is claimed is:
 1. A device comprising: a fin structure disposed ona substrate; a gate structure disposed over the fin structure, whereinthe gate structure includes: a gate dielectric layer disposed over thefin structure; a first layer disposed over the gate dielectric layer,the first layer having a first sidewall and a second opposing sidewallsuch that a bottom surface of the first layer extends from the firstsidewall to the second sidewall of the first layer; a growth controlmaterial disposed along the first sidewall of the first layer; and agate electrode fill material disposed on and physically contacting thegrowth control material and physically contacting the bottom surface ofthe first layer.
 2. The device of claim 1, wherein the first layerincludes a material selected from the group consisting of a metal oxideand a metal nitride.
 3. The device of claim 1, wherein the gateelectrode fill material is disposed between the growth control materialand the bottom surface of the first layer thereby preventing any portionof the growth control material from interfacing with the bottom surfaceof the first layer.
 4. The device of claim 1, wherein the growth controlextends to and physically contacts the bottom surface of the firstlayer.
 5. The device of claim 1, wherein the gate structure furtherincludes a work function layer disposed on the gate dielectric layersuch that the work function layer is disposed between the gatedielectric layer and the first layer.
 6. The device of claim 6, whereinthe gate structure further includes a barrier layer disposed on the workfunction layer such that the barrier layer is disposed between the workfunction layer and the first layer.
 7. The device of claim 1, whereinthe growth control material includes a material selected from the groupconsisting of WC, WN, AlC, and AN.
 8. A device comprising: a gatestructure disposed over a substrate, wherein the gate structureincludes: a first material layer having a first u-shaped profiledefining a recess, the material layer having a bottom surface; a growthcontrol material disposed within the recess, the growth control materialdecreasing in thickness as the growth control material extends towardsthe substrate; and a fill material disposed within recess and physicallycontain the growth control material and the bottom surface of the firstmaterial layer.
 9. The device of claim 8, wherein the gate structurefurther includes: a gate dielectric layer having a second u-shapedprofile; a work function layer having a third u-shaped profile; awetting layer having a fourth u-shaped profile, and wherein the firstmaterial layer is barrier layer.
 10. The device of claim 9, wherein thegate dielectric layer, the work function layer, the wetting layer, andthe barrier layer are formed of different materials.
 11. The device ofclaim 8, wherein the growth control material extends to and physicallycontacts the bottom surface of the first material layer.
 12. The deviceof claim 8, wherein the growth control material does not physicallycontact the bottom surface of the first material layer.
 13. The deviceof claim 8, wherein the first material layer, the growth controlmaterial and the fill material extend to the same height over thesubstrate.
 14. The device of claim 8, wherein the first material layerincludes an oxide material.
 15. A device comprising: a gate structuredisposed over a semiconductor substrate, wherein the gate structureincludes: a gate dielectric layer disposed over the semiconductorsubstrate; a barrier layer disposed over the gate dielectric layer, thebarrier layer having a first sidewall and a second opposing sidewallsuch that a bottom surface of the barrier layer extends from the firstsidewall to the second sidewall of the barrier layer; a growth controlmaterial disposed along the first sidewall of the barrier layer; and agate electrode fill material disposed on the growth control material anddisposed directly on a first portion of the bottom surface of thebarrier layer.
 16. The device of claim 15, wherein the growth controlmaterial is disposed directly on a second portion of the bottom surfaceof the barrier layer.
 17. The device of claim 15, wherein the gateelectrode fill material has a first width along an upper portion of thegate structure and a second width along a lower portion of the gatestructure, the first width being different than the second width. 18.The device of claim 15, wherein the gate structure further includes: awork function metal layer disposed directly on the gate dielectriclayer; and a wetting layer disposed directly on the work function metallayer.
 19. The device of claim 18, wherein the barrier layer is disposeddirectly on the wetting layer.
 20. The device of claim 15, wherein thewidth of the growth control material decreases as the growth controlmaterial extends along the first sidewall of the barrier layer towardthe bottom surface of the barrier layer.